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XAP Processors

XAP® is a family of portable processor IP cores

The XAP family of processors is optimised for low energy, low cost and easy verification. It is easy to design and verify chips that contain multiple XAP cores.

Our XAP® processor cores are Von Neumann RISC processors, combining high code density and excellent performance with simplicity of memory system design. Clearly defined software operating modes support modern RTOS features and provide an efficient and secure application platform.

Designers have a choice of processors.

Processor

Bus Width

Max Memory

DMIPS/MHz

Pipeline Stages

Gates
XAP4 16-bit 64 kB 0.95 2 12k
XAP5 16-bit 16 MB 0.93 2 18k
XAP6 32-bit 4 GB 1.36 3 30k

A wide range of data types and program sizes are managed efficiently and economically. XAP processors provide a complete execution platform for programs, typically written in the C language, using 8, 16 or 32-bit data types with library support for longer integers and floating point data. Their modern instruction set architecture delivers high performance and industry-leading code density, thereby minimising memory size, silicon cost and energy consumption.

These XAP cores use a single flat memory map to simplify ASIC design with security and reliability benefits, especially when programs are in re-programmable Flash or OTP memory.

Pick the right XAP for your application

XAP processors are designed for applications that require efficient data processing with low energy consumption at low cost. Choice of processor is determined by the memory system, which is governed by the application's program size and data requirements.

The pipeline stages are optimised to minimise energy usage whilst achieving best in class performance.

XAP's high code density paired with efficient stack and register usage minimises both program and data memory size and cost. XAP processors possess additional features to optimise security and reliability, especially with non-volatile memories such as Flash or OTP, as well as ROM and RAM.

There are three XAP processors to cope with a range of processing requirements.

XAP4 is a pure 16-bit processor with the smallest gate count. It supports 64 kB of memory. 

XAP5 is a 16/32-bit processor combing efficient 16-bit register operations with the ability to access a full 24-bit address space for larger software applications. A popular software option in C is to use 16-bit data pointers with 32-bit function pointers. It supports 16 MB of memory.

XAP6 is a pure 32-bit processor making it ideal for larger software systems which must integrate imported libraries and many modules from large software teams. It supports 4 GB of memory.

XAP hardware cores and customisable peripherals

XAP processor IP is delivered as soft core portable Verilog RTL that can be synthesised to a wide variety of digital libraries and semiconductor processes, giving licensee's full control over simulation and synthesis to optimise die area and power consumption.

XAP hardware includes an Interrupt Vector Controller, a Memory Management Unit, a Custom Logic Unit and a SIF debug interface. ASIC designers can customise the IVC, MMU and CLU for their particular system requirements.

The IVC supports a variety of prioritised and nested interrupts. The MMU can customise the address map and access to memory and I/O registers. The designer can create custom instructions in the CLU, with direct input and output access to the 8 general-purpose registers.

SIF is Cambridge Consultants’ patented debug interface that provides non-invasive access to memory and registers. This provides a valuable resource for debug and data logging in single and multi-processor systems.

XAP history

Cambridge Consultants has been designing processor cores since the early 1990s. XAP has been used in Bluetooth, BLE and WiFi products from CSR (Cambridge Silicon Radio), in ZigBee products from SiLabs and GreenPeak, in implantable wireless pacemakers from EBR, in touch-screen controllers from 3M and in many other ICs. More than two billion XAP processors have now been shipped in silicon.